CPU64 ----- This document was created by IDE64 Project team. Webpage: http://www.ide64.org Copyright 2004, 2005 Tomas Pribyl and Josef Soucek DRAFT revision: 5 January 2005 ------------------------------------ The Base CPU core ------------- Glossary -------- Internal processor, memory, IO - C64 internal External processor, memory, IO - components outside the C64 Introduction ----------------- CPU accelerator with IDE interface for C64. - Not another SuperCPU, not CommodoreONE, C64 compatibility is the main intention. - CPU implementaiton, instruction set compatible with 6510, cycle exact - CPU memory space increased to 16MB - implementation of the instruction for access to all memory space - maximum compatibility with SW for SCPU - implementation of PEROM 512kB (min. access time 70ns) - implementation of RAM 512kB (min access time 55ns/70ns) - updating of the SW in PEROM (IDEDOS+CPU core) by user form C64 - maximum compatibility with SW for current IDE64 Implementation proposal ------------------------------------ Project will implement CPU 6510 core with increased instruction set for access to 16MB address space, IDE interface SW compatible with current IDE64. Memory PEROM512kB AT29C040A, increased RAM512kB with the possible expansion. Real time clock chip DS1302 backed by battery and possibly simple USB 2.0 device controller. For the CPU, Altera ACEX1K30 or ACEX1K50. Configuration file for the FPGA is max to 98kB (1K50) and it will be stored with the SW in PEROM. For the initial configuration CPLD chip will be used (Mach M4A5 or similar), which will control the basic functions before the FPGA configuration. Max. frequency of the CPU is 14,2 MHz because of FPGA speed and access time to PEROM. As USB controller FDTI DS245B should be used. Description ----------------- IO space of the internal processor will be increased using CPLD Mach: - configuration register FPGA (R/W) - initialization register FPGA (WO) - memory management A14-A19 of the PEROM (WO) - register of the memory comfiguration After the power-on the 8kB configuration is enabled. $8000-$9fff is the page #0 from the last bank of the PEROM (ROM7). CPU detect the CBM80. If the PEROM is cleaned, the basic enviroment starts. PEROM programming -------------------------------- =Not translated yet= The time for FPGA configuration is estimated to 2-3 sec. After the configuration FPGA will start to work. Access to IO ------------------- The access to IO is divided to 3 types: 1 The handling of VIC, SID, CIA1, CIA2 (CHAROM is not available, it's not possible to switch $01 of the internal CPU). In this case the access to C64 is like access into slow peripheral. FPGA will do all cycles of the instruction fast, only the access cycle will be prolonged to the time of original FI2 with the respect of the VIC signal BA. 2 The handling of external peripherals IO1, IO2 FPGA do all cycles of the instruction fast, reading and writing cycle is the same 'size' as original FI2. No respect of BA. 3 The handling of the memory mapped to IO We use this area as normal memory so the cycle should not to be slow down (hold on?). The question is if the CPU mode will be used, because there are long instructions for jump into another bank. Access to memory --------------------------- When reading from the memory the cycle isn't synchronized with FI2, because the reading is from external RAM. When writing to the memory, the cycle is synchronized with FI2 and BA, but only according to set-up mirroring. The mirroring will be the same or very similar to SuperCPU. Instruction set ========== How the 65C816 addresing works ------------------------------------------------ For the program fetch the address is assembled from the PC(16bit) and PBR(8bit). For the manipulation with the data, the address is assembled form the PC(16bit) and DBR(8bit). (Not sure yet) PBR sets only these instructions: PLK - POP PBR from stack JMP - long JMP JML - JMP indirect long JSL - long JSR RTL - long RTS How is the higher banks handling in 65C816? ----------------------------------------------------------------- =Not translated yet= Which long instruction to implement? ------------------------------------------------------ - ABSOLUTE LONG (ORA,AND,EOR,LDA,STA,CMP,SBC,ADC,JMP) - ABSOLUTE LONG,X (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC) - STACK (PHB=>push DBR, PHK=>push PBR, PLB=>pop DBR, PLK=>pop PBR) We should to implement some instruction or function which can be used to identify the CPU "core" version. (The instruction set can change in the future) For jumping between memory banks we should used Long LMP instruction which sets PBR (ADR[23..16]) so the code will continue in the next 64kB page. Interrupts -------------- If the interrupt in B0 is handled, everithing goes the standard way. If the interrupt is handled in higher banks, the CPU will store PBR into stack and set the special IRQ-16 bit in the status to reach the origin bank back after the interrupt finishes by RTI. Memory map -------------------- Address space is 16MB, tj. 256 banks (B0-255) x 64kB. In the address space there are PEROM 512kB (8 banks ROM0-ROM7) and RAM 512kB (8 banks RAM0-RAM7) The RAM is in the first 8 banks B0-B7, Second variant sestion is to give ROM0-ROM7 to B248-B255 B0 <- RAM0 or ROM0 depends on $01 and memory address B1 <- RAM1 B2 <- RAM2 B3 <- RAM3 B4 <- RAM4 B5 <- RAM5 B6 <- RAM6 B7 <- RAM7 B8 to B247 <- expandable B248 <- R0M0 B249 <- R0M1 B250 <- R0M2 B251 <- R0M3 B252 <- R0M4 B253 <- R0M5 B254 <- R0M6 B255 <- R0M7 -------------- The kernal of C64 will be modified a bit to jump into ROM bank when something special have to be server (IDE64 etc.) We are currently considering to add some easy kind of memory protection for IDE64 ram buffers. To be continued...